In digital signal processing it is sometimes necessary to invert digital signals. Such inversion is commonly required when carrying out addition in two'complement format. A conventional way of forming the inverse of a signal is to connect the line through an exclusive OR gate so that a control signal fed to the gate determines whether or not the digital signal is transmitted in its normal or inverted form. In CMOS technology such an exclusive OR gate normally requires implementation by use of six transistors. Consequently to cause inversion of a pair of signal lines may require twelve transistors.
It is an object of the present invention to provide simplified circuitry for effecting inversion of digital signals particularly with the use of fewer transistors.
When using an array of CMOS adders these may be arranged in a series of addition stages each acting on a plurality of parallel inputs. It is a known characteristic of CMOS adders that they cause inversion of the output relative to the input. Furthermore the function of each adder is independent of the stage in the array where an input is provided to the adder.
By use of the present invention inversion of signals of a pair of digital signal lines supplying such an array of processing elements can be effected by use of a simple cross-over switch. Such cross-over switches can be implemented by the use of as few as four transistors thereby requiring only two transistors per line as opposed to six transistors per line when exclusive OR gates are used.